1. Field of the Invention
This invention relates to a semiconductor integrated circuit device with elements isolated by trenches, and more particularly to a semiconductor integrated circuit device most suitable for semiconductor memory devices, such as NAND type E.sup.2 PROMs or NOR type E.sup.2 PROMs.
2. Description of the Related Art
NAND type E.sup.2 PROMs have been constructed as shown in FIGS. 1 to 4, for example. FIG. 1 is a circuit diagram of a memory cell section in a NAND type E.sup.2 PROM. FIG. 2 is a pattern plan view of the circuit shown in FIG. 1. FIG. 3 is a sectional view taken along line 3--3 in the pattern of FIG. 2. FIG. 4 is a sectional view taken along line 4--4 in the pattern of FIG. 2 together with a cross section of adjoining memory cell portions. This type of NAND E.sup.2 PROM has been disclosed in, for example, U.S. Pat. No. 4,996,669, U.S. Pat. No. 5,088,060, U.S. Pat. No. 4,959,812, and U.S. Pat. No. 5,050,125.
As shown in FIG. 1, with the memory cells in the NAND type E.sup.2 PROM, the respective current paths of a cell select MOS transistor 12-1, cell transistors 13-1 to 13-8, and a cell select MOS transistor 12-2 are connected in series between a bit line 11 and a power supply Vss (a grounding point or a reference potential supply). The gates of the MOS transistors 12-1, 12-2 are supplied with select signals SG1, SG2, respectively. When these MOS transistors 12-1, 12-2 are turned on, the memory cell section is selected. The control gates of the individual cell transistors 13-1 to 13-8 are connected to word lines. By the row select signals CG1 to CG8 outputted from a row decoder, any one of the cell transistors is selected and then the data is programmed or read out.
As shown in FIGS. 2 to 4, the memory cell section is formed in a p-well region 15 formed in the surface region of an n-type semiconductor substrate 14. The MOS transistor 12-1, the individual cell transistors 13-1 to 13-8, and the MOS transistor 12-2 each share drain regions and source regions with the adjoining transistors. On the substrate 14 between the drain and source regions of the individual cell transistors 13-1 to 13-8, first gate insulating films 16-1 to 16-8 through which tunnel current flows, floating gates 17-1 to 17-8, second insulating films 18-1 to 18-8, and control gates 19-1 to 19-8 are stacked one on top of another in that order. The MOS transistors 12-1, 12-2 are formed in the same process as the cell transistors 13-1 to 13-8. Although they have floating gates and control gates, short-circuiting these gates enables them to function as cell select MOS transistors. On the individual transistors 12-1, 13-1 to 13-8, 12-2, an interlayer insulating film 20 is formed. On the interlayer insulating film 20, the bit line 11 is placed. The bit line 11 is formed in the direction in which the current paths of the cell transistors 13-1 to 13-8 are connected in series, and is connected to the drain region 12-1D of the MOS transistor 12-1. On the other hand, the grounding point Vss is connected to the source region 12-2S of the MOS transistor 12-2.
With the NAND type E.sup.2 PROM thus constructed, a state where the threshold voltage (Vth) of the transistor is in the range from 0 V to 5 V as a result of injecting electrons into the floating gate, is defined as data "0", and a state where the threshold voltage is below 0 V is defined as data "1". At the time of programming, a high voltage of about 20 V is applied to the word line connected to the control gate of the selected cell transistor and 0 V is applied to the bit line. As a result of this, by an electric field (about 13 MVcm.sup.-1) with respect to the substrate caused by the potential (about 13 V) of the floating gate risen according to the coupling ratio of capacitance C1 between the control gate and the floating gate to capacitance C2 between the floating gate and the channel region, tunnel current is generated, thereby injecting electrons into the floating gate. At this time, an intermediate potential of about 12 V is applied to the unselected bit lines to prevent erroneous writing, thereby reducing the voltage difference between the floating gate and the substrate. Erasing is effected by applying a voltage of about 20 V to the substrate (normally, the p-type well region), thereby applying a high electric field to extract electrons from the floating gate. Since the NAND type E.sup.2 PROM is what is called a flash memory, all of the bits are erased at the same time or bits are erased in blocks. At this time, the floating gate is overerased and thereby charged positively, placing the cell transistor in the depletion mode. Reading to judge whether the stored data item is "1" or "0" is effected by setting the word line of the selected cell at 0 V and the bit line at 5 V, and the word lines of the unselected word lines at 5 V.
What has been explained above is about the basic principle of the NAND type E.sup.2 PROM. Because in the NAND type E.sup.2 PROM, the bit lines need not be brought into contact with the cell transistors on a one-to-one basis as shown in FIGS. 2 and 3, the number of contacts can be decreased as compared with the NOR type, leading to a smaller cell size.
NAND type E.sup.2 PROMs have lately attracted attention as devices that would replace HDDs (hard disk drives) in the future and therefore they have been requested to have a much larger capacity, be lower in cost, and be reduced further in cell size. In the present cell arrangement, however, as shown in the sectional view across the channel width in FIG. 4, the area of the element isolation region 21 (a field oxide film formed by LOCOS techniques) is larger than that of the cell transistor, and the area necessary for element isolation occupies three times as large as the area used for a tunneling phenomenon. Specifically, if the minimum design rule is .DELTA.t, the width of a first gate insulating film 16-6 through which tunnel current flows is .DELTA.t, whereas a width of .DELTA.t is required on both sides of the insulating film 16-6 when element isolating regions 21 are formed on both sides of the insulating film 16-6. Consequently, the width of the floating gate 17-6 is the value obtained by adding 2.DELTA.t to the width of the insulating film 16-6, that is, 3.DELTA.t. Since a space of .DELTA.t is needed between adjoining floating gates, 4.DELTA.t is required for the width T of a single cell transistor.
As noted above, with the conventional NAND type E.sup.2 PROM, the existence of element isolation regions forces the principle of "the minimum design rule.times.4" to be always followed in determining the cell size. To reduce the cell size remarkably in the future, the element isolation regions must be reduced considerably.
Other semiconductor storage devices and semiconductor integrated circuit devices, such as NOR type E.sup.2 PROMs have a similar problem as the aforementioned NAND type E.sup.2 PROM has, wherein the existence of element isolation regions prevents the reduction of chip size and high integration significantly.